/* Copyright (c) 2025 Beijing Semidrive Technology Corporation
 * SPDX-License-Identifier: Apache-2.0
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
 * you may not use this file except in compliance with the License.
 * You may obtain a copy of the License at
 *
 * http://www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an "AS IS" BASIS,
 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 * See the License for the specific language governing permissions and
 * limitations under the License.
 */
/*PRQA S 0791 EOF*/
/**
 * @file  SpiSlave_lave_reg.h
 * @brief Semidrive. AUTOSAR 4.3.1 MCAL SpiSlave_Slave plugins.
 */

/* Generated by tool. Do not modify manually. */

#ifndef SPI_SLV_REG_H
#define SPI_SLV_REG_H

#define SPI_CTRL_OFF  0x0U

#define BM_SPI_CTRL_SW_RST  ((uint32)0x01U << 31U)

#define FM_SPI_CTRL_IDLE  ((uint32)0x1fU << 25U)
#define FV_SPI_CTRL_IDLE(v) \
  (((uint32)(v) << 25U) & FM_SPI_CTRL_IDLE)
#define GFV_SPI_CTRL_IDLE(v) \
  (((uint32)(v) & FM_SPI_CTRL_IDLE) >> 25U)

#define BM_SPI_CTRL_SW_NSS_TRIGGER  ((uint32)0x01U << 22U)

#define BM_SPI_CTRL_NSS_MODE  ((uint32)0x01U << 21U)

#define FM_SPI_CTRL_TIMEOUT  ((uint32)0x1fU << 16U)
#define FV_SPI_CTRL_TIMEOUT(v) \
  (((uint32)(v) << 16U) & FM_SPI_CTRL_TIMEOUT)
#define GFV_SPI_CTRL_TIMEOUT(v) \
  (((uint32)(v) & FM_SPI_CTRL_TIMEOUT) >> 16U)

#define FM_SPI_CTRL_NSS_POL  ((uint32)0x3fU << 8U)
#define FV_SPI_CTRL_NSS_POL(v) \
  (((uint32)(v) << 8U) & FM_SPI_CTRL_NSS_POL)
#define GFV_SPI_CTRL_NSS_POL(v) \
  (((uint32)(v) & FM_SPI_CTRL_NSS_POL) >> 8U)

#define BM_SPI_CTRL_FRM_END_IRQ_MODE  ((uint32)0x01U << 7U)

#define BM_SPI_CTRL_SSP_CLK_MODE  ((uint32)0x01U << 6U)

#define BM_SPI_CTRL_RX_DMA_EN  ((uint32)0x01U << 5U)

#define BM_SPI_CTRL_TX_DMA_EN  ((uint32)0x01U << 4U)

#define BM_SPI_CTRL_SLV_MODE  ((uint32)0x01U << 3U)

#define BM_SPI_CTRL_HALF_MODE  ((uint32)0x01U << 2U)

#define BM_SPI_CTRL_SLV_UNS_SIZE_EN  ((uint32)0x01U << 1U)

#define BM_SPI_CTRL_MODE  ((uint32)0x01U << 0U)

#define SPI_TIM_CTRL_OFF  0x4U

#define FM_SPI_TIM_CTRL_FH_DLY  ((uint32)0xffU << 24U)
#define FV_SPI_TIM_CTRL_FH_DLY(v) \
  (((uint32)(v) << 24U) & FM_SPI_TIM_CTRL_FH_DLY)
#define GFV_SPI_TIM_CTRL_FH_DLY(v) \
  (((uint32)(v) & FM_SPI_TIM_CTRL_FH_DLY) >> 24U)

#define FM_SPI_TIM_CTRL_FRM_DLY  ((uint32)0xffU << 16U)
#define FV_SPI_TIM_CTRL_FRM_DLY(v) \
  (((uint32)(v) << 16U) & FM_SPI_TIM_CTRL_FRM_DLY)
#define GFV_SPI_TIM_CTRL_FRM_DLY(v) \
  (((uint32)(v) & FM_SPI_TIM_CTRL_FRM_DLY) >> 16U)

#define FM_SPI_TIM_CTRL_END_DLY  ((uint32)0xffU << 8U)
#define FV_SPI_TIM_CTRL_END_DLY(v) \
  (((uint32)(v) << 8U) & FM_SPI_TIM_CTRL_END_DLY)
#define GFV_SPI_TIM_CTRL_END_DLY(v) \
  (((uint32)(v) & FM_SPI_TIM_CTRL_END_DLY) >> 8U)

#define FM_SPI_TIM_CTRL_START_DLY  ((uint32)0xffU << 0U)
#define FV_SPI_TIM_CTRL_START_DLY(v) \
  (((uint32)(v) << 0U) & FM_SPI_TIM_CTRL_START_DLY)
#define GFV_SPI_TIM_CTRL_START_DLY(v) \
  (((uint32)(v) & FM_SPI_TIM_CTRL_START_DLY) >> 0U)

#define SPI_EN_OFF  0x8U

#define BM_SPI_EN_ENABLE  ((uint32)0x01U << 0U)

#define SPI_DEBUG_CTRL_OFF  0xcU

#define BM_SPI_DEBUG_CTRL_DEBUG_MODE_RX_FIFO_RD_EN  ((uint32)0x01U << 2U)

#define BM_SPI_DEBUG_CTRL_DEBUG_MODE_CTRL  ((uint32)0x01U << 1U)

#define BM_SPI_DEBUG_CTRL_DEBUG_MODE_SW_EN  ((uint32)0x01U << 0U)

#define SPI_CMD_CTRL_OFF  0x10U

#define FM_SPI_CMD_CTRL_PRESSCALE  ((uint32)0xffU << 24U)
#define FV_SPI_CMD_CTRL_PRESSCALE(v) \
  (((uint32)(v) << 24U) & FM_SPI_CMD_CTRL_PRESSCALE)
#define GFV_SPI_CMD_CTRL_PRESSCALE(v) \
  (((uint32)(v) & FM_SPI_CMD_CTRL_PRESSCALE) >> 24U)

#define BM_SPI_CMD_CTRL_TX_MASK  ((uint32)0x01U << 23U)

#define BM_SPI_CMD_CTRL_RX_MASK  ((uint32)0x01U << 22U)

#define FM_SPI_CMD_CTRL_FRAM_SIZE  ((uint32)0x3ffU << 12U)
#define FV_SPI_CMD_CTRL_FRAM_SIZE(v) \
  (((uint32)(v) << 12U) & FM_SPI_CMD_CTRL_FRAM_SIZE)
#define GFV_SPI_CMD_CTRL_FRAM_SIZE(v) \
  (((uint32)(v) & FM_SPI_CMD_CTRL_FRAM_SIZE) >> 12U)

#define FM_SPI_CMD_CTRL_WORD_SIZE  ((uint32)0x1fU << 7U)
#define FV_SPI_CMD_CTRL_WORD_SIZE(v) \
  (((uint32)(v) << 7U) & FM_SPI_CMD_CTRL_WORD_SIZE)
#define GFV_SPI_CMD_CTRL_WORD_SIZE(v) \
  (((uint32)(v) & FM_SPI_CMD_CTRL_WORD_SIZE) >> 7U)

#define BM_SPI_CMD_CTRL_SPI_CPHA  ((uint32)0x01U << 6U)

#define BM_SPI_CMD_CTRL_SPI_CPOL  ((uint32)0x01U << 5U)

#define BM_SPI_CMD_CTRL_LAST  ((uint32)0x01U << 4U)

#define BM_SPI_CMD_CTRL_NSS_BIT2  ((uint32)0x01U << 3U)

#define BM_SPI_CMD_CTRL_LSB  ((uint32)0x01U << 2U)

#define FM_SPI_CMD_CTRL_NSS  ((uint32)0x3U << 0U)
#define FV_SPI_CMD_CTRL_NSS(v) \
  (((uint32)(v) << 0U) & FM_SPI_CMD_CTRL_NSS)
#define GFV_SPI_CMD_CTRL_NSS(v) \
  (((uint32)(v) & FM_SPI_CMD_CTRL_NSS) >> 0U)

#define SPI_CTRL2_OFF  0x14U

#define BM_SPI_CTRL2_TIME_OUT_CLEAR  ((uint32)0x01U << 9U)

#define BM_SPI_CTRL2_SWAP  ((uint32)0x01U << 8U)

#define BM_SPI_CTRL2_CMD_MASK  ((uint32)0x01U << 7U)

#define BM_SPI_CTRL2_LOOP_BACK_MODE  ((uint32)0x01U << 6U)

#define BM_SPI_CTRL2_TX_DMA_REQ_EN  ((uint32)0x01U << 5U)

#define BM_SPI_CTRL2_FRM_CS_EN  ((uint32)0x01U << 4U)

#define BM_SPI_CTRL2_TIMEOUT_EN  ((uint32)0x01U << 3U)

#define FM_SPI_CTRL2_SAMPLE_POINT  ((uint32)0x7U << 0U)
#define FV_SPI_CTRL2_SAMPLE_POINT(v) \
  (((uint32)(v) << 0U) & FM_SPI_CTRL2_SAMPLE_POINT)
#define GFV_SPI_CTRL2_SAMPLE_POINT(v) \
  (((uint32)(v) & FM_SPI_CTRL2_SAMPLE_POINT) >> 0U)

#define SPI_STAT_OFF  0x18U

#define FM_SPI_STAT_SLV_UNS_TX_NUM  ((uint32)0xffffU << 0U)
#define FV_SPI_STAT_SLV_UNS_TX_NUM(v) \
  (((uint32)(v) << 0U) & FM_SPI_STAT_SLV_UNS_TX_NUM)
#define GFV_SPI_STAT_SLV_UNS_TX_NUM(v) \
  (((uint32)(v) & FM_SPI_STAT_SLV_UNS_TX_NUM) >> 0U)

#define SPI_IRQ_MASK_OFF  0x20U

#define BM_SPI_IRQ_MASK_PARITY_BIT_ERR  ((uint32)0x01U << 18U)

#define BM_SPI_IRQ_MASK_SCK_BAUD_ERR  ((uint32)0x01U << 17U)

#define BM_SPI_IRQ_MASK_END_DLY_ERR  ((uint32)0x01U << 16U)

#define BM_SPI_IRQ_MASK_START_DLY_ERR  ((uint32)0x01U << 15U)

#define BM_SPI_IRQ_MASK_MST_FRM_END  ((uint32)0x01U << 14U)

#define BM_SPI_IRQ_MASK_SLV_NSS_INVLD  ((uint32)0x01U << 13U)

#define BM_SPI_IRQ_MASK_SLV_NSS_VLD  ((uint32)0x01U << 12U)

#define BM_SPI_IRQ_MASK_IDLE  ((uint32)0x01U << 11U)

#define BM_SPI_IRQ_MASK_TIMEOUT  ((uint32)0x01U << 10U)

#define BM_SPI_IRQ_MASK_TRANS_DONE  ((uint32)0x01U << 9U)

#define BM_SPI_IRQ_MASK_FRM_DONE  ((uint32)0x01U << 8U)

#define BM_SPI_IRQ_MASK_RX_FIFO_PRE_FULL  ((uint32)0x01U << 7U)

#define BM_SPI_IRQ_MASK_TX_FIFO_PRE_EMPTY  ((uint32)0x01U << 6U)

#define BM_SPI_IRQ_MASK_RX_FIFO_OVR  ((uint32)0x01U << 5U)

#define BM_SPI_IRQ_MASK_RX_FIFO_FULL  ((uint32)0x01U << 4U)

#define BM_SPI_IRQ_MASK_RX_FIFO_EMPTY  ((uint32)0x01U << 3U)

#define BM_SPI_IRQ_MASK_TX_FIFO_UDR  ((uint32)0x01U << 2U)

#define BM_SPI_IRQ_MASK_TX_FIFO_FULL  ((uint32)0x01U << 1U)

#define BM_SPI_IRQ_MASK_TX_FIFO_EMPTY  ((uint32)0x01U << 0U)

#define SPI_IRQ_STAT_OFF  0x24U

#define FM_SPI_IRQ_STAT_SPI_FSM_ST  ((uint32)0x1fU << 27U)
#define FV_SPI_IRQ_STAT_SPI_FSM_ST(v) \
  (((uint32)(v) << 27U) & FM_SPI_IRQ_STAT_SPI_FSM_ST)
#define GFV_SPI_IRQ_STAT_SPI_FSM_ST(v) \
  (((uint32)(v) & FM_SPI_IRQ_STAT_SPI_FSM_ST) >> 27U)

#define BM_SPI_IRQ_STAT_PARITY_BIT_ERR  ((uint32)0x01U << 18U)

#define BM_SPI_IRQ_STAT_SCK_BAUD_ERR  ((uint32)0x01U << 17U)

#define BM_SPI_IRQ_STAT_END_DLY_ERR  ((uint32)0x01U << 16U)

#define BM_SPI_IRQ_STAT_START_DLY_ERR  ((uint32)0x01U << 15U)

#define BM_SPI_IRQ_STAT_MST_FRM_END  ((uint32)0x01U << 14U)

#define BM_SPI_IRQ_STAT_SLV_NSS_INVLD  ((uint32)0x01U << 13U)

#define BM_SPI_IRQ_STAT_SLV_NSS_VLD  ((uint32)0x01U << 12U)

#define BM_SPI_IRQ_STAT_IDLE  ((uint32)0x01U << 11U)

#define BM_SPI_IRQ_STAT_TIMEOUT  ((uint32)0x01U << 10U)

#define BM_SPI_IRQ_STAT_TRANS_DONE  ((uint32)0x01U << 9U)

#define BM_SPI_IRQ_STAT_FRM_DONE  ((uint32)0x01U << 8U)

#define BM_SPI_IRQ_STAT_RX_FIFO_PRE_FULL  ((uint32)0x01U << 7U)

#define BM_SPI_IRQ_STAT_TX_FIFO_PRE_EMPTY  ((uint32)0x01U << 6U)

#define BM_SPI_IRQ_STAT_RX_FIFO_OVR  ((uint32)0x01U << 5U)

#define BM_SPI_IRQ_STAT_RX_FIFO_FULL  ((uint32)0x01U << 4U)

#define BM_SPI_IRQ_STAT_RX_FIFO_EMPTY  ((uint32)0x01U << 3U)

#define BM_SPI_IRQ_STAT_TX_FIFO_UDR  ((uint32)0x01U << 2U)

#define BM_SPI_IRQ_STAT_TX_FIFO_FULL  ((uint32)0x01U << 1U)

#define BM_SPI_IRQ_STAT_TX_FIFO_EMPTY  ((uint32)0x01U << 0U)

#define SPI_FIFO_STAT_OFF  0x30U

#define BM_SPI_FIFO_STAT_RX_FULL  ((uint32)0x01U << 25U)

#define BM_SPI_FIFO_STAT_RX_EMPTY  ((uint32)0x01U << 24U)

#define FM_SPI_FIFO_STAT_RX_FIFO_DPTR  ((uint32)0x1fU << 16U)
#define FV_SPI_FIFO_STAT_RX_FIFO_DPTR(v) \
  (((uint32)(v) << 16U) & FM_SPI_FIFO_STAT_RX_FIFO_DPTR)
#define GFV_SPI_FIFO_STAT_RX_FIFO_DPTR(v) \
  (((uint32)(v) & FM_SPI_FIFO_STAT_RX_FIFO_DPTR) >> 16U)

#define BM_SPI_FIFO_STAT_TX_FULL  ((uint32)0x01U << 9U)

#define BM_SPI_FIFO_STAT_TX_EMPTY  ((uint32)0x01U << 8U)

#define FM_SPI_FIFO_STAT_TX_FIFO_DPTR  ((uint32)0x1fU << 0U)
#define FV_SPI_FIFO_STAT_TX_FIFO_DPTR(v) \
  (((uint32)(v) << 0U) & FM_SPI_FIFO_STAT_TX_FIFO_DPTR)
#define GFV_SPI_FIFO_STAT_TX_FIFO_DPTR(v) \
  (((uint32)(v) & FM_SPI_FIFO_STAT_TX_FIFO_DPTR) >> 0U)

#define SPI_TX_FIFO_CTRL_OFF  0x34U

#define FM_SPI_TX_FIFO_CTRL_THRD  ((uint32)0xfU << 0U)
#define FV_SPI_TX_FIFO_CTRL_THRD(v) \
  (((uint32)(v) << 0U) & FM_SPI_TX_FIFO_CTRL_THRD)
#define GFV_SPI_TX_FIFO_CTRL_THRD(v) \
  (((uint32)(v) & FM_SPI_TX_FIFO_CTRL_THRD) >> 0U)

#define SPI_RX_FIFO_CTRL_OFF  0x38U

#define FM_SPI_RX_FIFO_CTRL_THRD  ((uint32)0xfU << 0U)
#define FV_SPI_RX_FIFO_CTRL_THRD(v) \
  (((uint32)(v) << 0U) & FM_SPI_RX_FIFO_CTRL_THRD)
#define GFV_SPI_RX_FIFO_CTRL_THRD(v) \
  (((uint32)(v) & FM_SPI_RX_FIFO_CTRL_THRD) >> 0U)

#define REG_PARITY_ERR_INT_STAT_OFF  0x40U

#define REG_PARITY_ERR_INT_SIG_EN_OFF  0x44U

#define FUSA_UNC_ERR_IRQ_STAT_OFF  0x48U

#define BM_FUSA_UNC_ERR_IRQ_STAT_DEBUG_MODE_CHECK_ERR  ((uint32)0x01U << 14U)

#define BM_FUSA_UNC_ERR_IRQ_STAT_RX_DMA_EOBA_POL_ERR  ((uint32)0x01U << 13U)

#define BM_FUSA_UNC_ERR_IRQ_STAT_RX_DMA_EOBC_POL_ERR  ((uint32)0x01U << 12U)

#define BM_FUSA_UNC_ERR_IRQ_STAT_RX_DMA_BW_FATAL_ERR  ((uint32)0x01U << 11U)

#define BM_FUSA_UNC_ERR_IRQ_STAT_RX_DMA_BW_UNC_ERR  ((uint32)0x01U << 10U)

#define BM_FUSA_UNC_ERR_IRQ_STAT_TX_DMA_EOBA_POL_ERR  ((uint32)0x01U << 9U)

#define BM_FUSA_UNC_ERR_IRQ_STAT_TX_DMA_EOBC_POL_ERR  ((uint32)0x01U << 8U)

#define BM_FUSA_UNC_ERR_IRQ_STAT_TX_DMA_BW_FATAL_ERR  ((uint32)0x01U << 7U)

#define BM_FUSA_UNC_ERR_IRQ_STAT_TX_DMA_BW_UNC_ERR  ((uint32)0x01U << 6U)

#define BM_FUSA_UNC_ERR_IRQ_STAT_ERR_INJ_EN_ERR  ((uint32)0x01U << 5U)

#define BM_FUSA_UNC_ERR_IRQ_STAT_REG_PARITY_ERR_INJ_EN_ERR  ((uint32)0x01U << 4U)

#define BM_FUSA_UNC_ERR_IRQ_STAT_PCTL_UNC_ERR  ((uint32)0x01U << 3U)

#define BM_FUSA_UNC_ERR_IRQ_STAT_PADDR_UNC_ERR  ((uint32)0x01U << 2U)

#define BM_FUSA_UNC_ERR_IRQ_STAT_PWDATA_FATAL_ERR  ((uint32)0x01U << 1U)

#define BM_FUSA_UNC_ERR_IRQ_STAT_PWDATA_UNC_ERR  ((uint32)0x01U << 0U)

#define FUSA_UNC_ERR_IRQ_MASK_OFF  0x4cU

#define BM_FUSA_UNC_ERR_IRQ_MASK_DEBUG_MODE_CHECK_ERR  ((uint32)0x01U << 14U)

#define BM_FUSA_UNC_ERR_IRQ_MASK_RX_DMA_EOBA_POL_ERR  ((uint32)0x01U << 13U)

#define BM_FUSA_UNC_ERR_IRQ_MASK_RX_DMA_EOBC_POL_ERR  ((uint32)0x01U << 12U)

#define BM_FUSA_UNC_ERR_IRQ_MASK_RX_DMA_BW_FATAL_ERR  ((uint32)0x01U << 11U)

#define BM_FUSA_UNC_ERR_IRQ_MASK_RX_DMA_BW_UNC_ERR  ((uint32)0x01U << 10U)

#define BM_FUSA_UNC_ERR_IRQ_MASK_TX_DMA_EOBA_POL_ERR  ((uint32)0x01U << 9U)

#define BM_FUSA_UNC_ERR_IRQ_MASK_TX_DMA_EOBC_POL_ERR  ((uint32)0x01U << 8U)

#define BM_FUSA_UNC_ERR_IRQ_MASK_TX_DMA_BW_FATAL_ERR  ((uint32)0x01U << 7U)

#define BM_FUSA_UNC_ERR_IRQ_MASK_TX_DMA_BW_UNC_ERR  ((uint32)0x01U << 6U)

#define BM_FUSA_UNC_ERR_IRQ_MASK_ERR_INJ_EN_ERR  ((uint32)0x01U << 5U)

#define BM_FUSA_UNC_ERR_IRQ_MASK_REG_PARITY_ERR_INJ_EN_ERR  ((uint32)0x01U << 4U)

#define BM_FUSA_UNC_ERR_IRQ_MASK_PCTL_UNC_ERR  ((uint32)0x01U << 3U)

#define BM_FUSA_UNC_ERR_IRQ_MASK_PADDR_UNC_ERR  ((uint32)0x01U << 2U)

#define BM_FUSA_UNC_ERR_IRQ_MASK_PWDATA_FATAL_ERR  ((uint32)0x01U << 1U)

#define BM_FUSA_UNC_ERR_IRQ_MASK_PWDATA_UNC_ERR  ((uint32)0x01U << 0U)

#define FUSA_COR_ERR_IRQ_STAT_OFF  0x50U

#define BM_FUSA_COR_ERR_IRQ_STAT_RX_DMA_BW_COR_ERR  ((uint32)0x01U << 2U)

#define BM_FUSA_COR_ERR_IRQ_STAT_TX_DMA_BW_COR_ERR  ((uint32)0x01U << 1U)

#define BM_FUSA_COR_ERR_IRQ_STAT_PWDATA_COR_ERR  ((uint32)0x01U << 0U)

#define FUSA_COR_ERR_IRQ_MASK_OFF  0x54U

#define BM_FUSA_COR_ERR_IRQ_MASK_RX_DMA_BW_COR_ERR  ((uint32)0x01U << 2U)

#define BM_FUSA_COR_ERR_IRQ_MASK_TX_DMA_BW_COR_ERR  ((uint32)0x01U << 1U)

#define BM_FUSA_COR_ERR_IRQ_MASK_PWDATA_COR_ERR  ((uint32)0x01U << 0U)

#define PWDATA_INJ_OFF  0x58U

#define PWECC_INJ_OFF  0x5cU

#define PRDATAINJ_OFF  0x60U

#define INT_ERR_INJ_OFF  0x64U

#define BM_INT_ERR_INJ_FUN_IRQ  ((uint32)0x01U << 0U)

#define DMA_INJ_OFF  0x68U

#define FM_DMA_INJ_RX_FW_DATA_INJ  ((uint32)0xfU << 28U)
#define FV_DMA_INJ_RX_FW_DATA_INJ(v) \
  (((uint32)(v) << 28U) & FM_DMA_INJ_RX_FW_DATA_INJ)
#define GFV_DMA_INJ_RX_FW_DATA_INJ(v) \
  (((uint32)(v) & FM_DMA_INJ_RX_FW_DATA_INJ) >> 28U)

#define FM_DMA_INJ_RX_FW_CODE_INJ  ((uint32)0xfU << 24U)
#define FV_DMA_INJ_RX_FW_CODE_INJ(v) \
  (((uint32)(v) << 24U) & FM_DMA_INJ_RX_FW_CODE_INJ)
#define GFV_DMA_INJ_RX_FW_CODE_INJ(v) \
  (((uint32)(v) & FM_DMA_INJ_RX_FW_CODE_INJ) >> 24U)

#define FM_DMA_INJ_RX_BW_DATA_INJ  ((uint32)0xfU << 20U)
#define FV_DMA_INJ_RX_BW_DATA_INJ(v) \
  (((uint32)(v) << 20U) & FM_DMA_INJ_RX_BW_DATA_INJ)
#define GFV_DMA_INJ_RX_BW_DATA_INJ(v) \
  (((uint32)(v) & FM_DMA_INJ_RX_BW_DATA_INJ) >> 20U)

#define FM_DMA_INJ_RX_BW_CODE_INJ  ((uint32)0xfU << 16U)
#define FV_DMA_INJ_RX_BW_CODE_INJ(v) \
  (((uint32)(v) << 16U) & FM_DMA_INJ_RX_BW_CODE_INJ)
#define GFV_DMA_INJ_RX_BW_CODE_INJ(v) \
  (((uint32)(v) & FM_DMA_INJ_RX_BW_CODE_INJ) >> 16U)

#define FM_DMA_INJ_TX_FW_DATA_INJ  ((uint32)0xfU << 12U)
#define FV_DMA_INJ_TX_FW_DATA_INJ(v) \
  (((uint32)(v) << 12U) & FM_DMA_INJ_TX_FW_DATA_INJ)
#define GFV_DMA_INJ_TX_FW_DATA_INJ(v) \
  (((uint32)(v) & FM_DMA_INJ_TX_FW_DATA_INJ) >> 12U)

#define FM_DMA_INJ_TX_FW_CODE_INJ  ((uint32)0xfU << 8U)
#define FV_DMA_INJ_TX_FW_CODE_INJ(v) \
  (((uint32)(v) << 8U) & FM_DMA_INJ_TX_FW_CODE_INJ)
#define GFV_DMA_INJ_TX_FW_CODE_INJ(v) \
  (((uint32)(v) & FM_DMA_INJ_TX_FW_CODE_INJ) >> 8U)

#define FM_DMA_INJ_TX_BW_DATA_INJ  ((uint32)0xfU << 4U)
#define FV_DMA_INJ_TX_BW_DATA_INJ(v) \
  (((uint32)(v) << 4U) & FM_DMA_INJ_TX_BW_DATA_INJ)
#define GFV_DMA_INJ_TX_BW_DATA_INJ(v) \
  (((uint32)(v) & FM_DMA_INJ_TX_BW_DATA_INJ) >> 4U)

#define FM_DMA_INJ_TX_BW_CODE_INJ  ((uint32)0xfU << 0U)
#define FV_DMA_INJ_TX_BW_CODE_INJ(v) \
  (((uint32)(v) << 0U) & FM_DMA_INJ_TX_BW_CODE_INJ)
#define GFV_DMA_INJ_TX_BW_CODE_INJ(v) \
  (((uint32)(v) & FM_DMA_INJ_TX_BW_CODE_INJ) >> 0U)

#define PTY_BIT_CTL_OFF  0x70U

#define BM_PTY_BIT_CTL_RX_PARITY_TYPE  ((uint32)0x01U << 3U)

#define BM_PTY_BIT_CTL_TX_PARITY_TYPE  ((uint32)0x01U << 2U)

#define BM_PTY_BIT_CTL_RX_PARITY_EN  ((uint32)0x01U << 1U)

#define BM_PTY_BIT_CTL_TX_PARITY_EN  ((uint32)0x01U << 0U)

#define PTY_TIM_ERR_UNC_STAT_OFF  0x74U

#define BM_PTY_TIM_ERR_UNC_STAT_PARITY_BIT_ERR  ((uint32)0x01U << 3U)

#define BM_PTY_TIM_ERR_UNC_STAT_SCK_BAUD_ERR  ((uint32)0x01U << 2U)

#define BM_PTY_TIM_ERR_UNC_STAT_END_DLY_ERR  ((uint32)0x01U << 1U)

#define BM_PTY_TIM_ERR_UNC_STAT_START_DLY_ERR  ((uint32)0x01U << 0U)

#define PTY_TIM_ERR_UNC_MASK_OFF  0x78U

#define BM_PTY_TIM_ERR_UNC_MASK_PARITY_BIT_MASK_UNC_IRQ  ((uint32)0x01U << 3U)

#define BM_PTY_TIM_ERR_UNC_MASK_SCK_BAUD_ERR_MASK_UNC_IRQ  ((uint32)0x01U << 2U)

#define BM_PTY_TIM_ERR_UNC_MASK_END_DLY_ERR_MASK_UNC_IRQ  ((uint32)0x01U << 1U)

#define BM_PTY_TIM_ERR_UNC_MASK_START_DLY_ERR_MASK_UNC_IRQ  ((uint32)0x01U << 0U)

#define SELFTEST_MODE_OFF  0x80U

#define SPI_START_CHK_OFF  0x90U

#define FM_SPI_START_CHK_UPPER_LIMIT  ((uint32)0xffffU << 16U)
#define FV_SPI_START_CHK_UPPER_LIMIT(v) \
  (((uint32)(v) << 16U) & FM_SPI_START_CHK_UPPER_LIMIT)
#define GFV_SPI_START_CHK_UPPER_LIMIT(v) \
  (((uint32)(v) & FM_SPI_START_CHK_UPPER_LIMIT) >> 16U)

#define FM_SPI_START_CHK_LOWER_LIMIT  ((uint32)0xffffU << 0U)
#define FV_SPI_START_CHK_LOWER_LIMIT(v) \
  (((uint32)(v) << 0U) & FM_SPI_START_CHK_LOWER_LIMIT)
#define GFV_SPI_START_CHK_LOWER_LIMIT(v) \
  (((uint32)(v) & FM_SPI_START_CHK_LOWER_LIMIT) >> 0U)

#define SPI_END_CHK_OFF  0x94U

#define FM_SPI_END_CHK_UPPER_LIMIT  ((uint32)0xffffU << 16U)
#define FV_SPI_END_CHK_UPPER_LIMIT(v) \
  (((uint32)(v) << 16U) & FM_SPI_END_CHK_UPPER_LIMIT)
#define GFV_SPI_END_CHK_UPPER_LIMIT(v) \
  (((uint32)(v) & FM_SPI_END_CHK_UPPER_LIMIT) >> 16U)

#define FM_SPI_END_CHK_LOWER_LIMIT  ((uint32)0xffffU << 0U)
#define FV_SPI_END_CHK_LOWER_LIMIT(v) \
  (((uint32)(v) << 0U) & FM_SPI_END_CHK_LOWER_LIMIT)
#define GFV_SPI_END_CHK_LOWER_LIMIT(v) \
  (((uint32)(v) & FM_SPI_END_CHK_LOWER_LIMIT) >> 0U)

#define SPI_SCK_CHK_OFF  0x98U

#define FM_SPI_SCK_CHK_UPPER_LIMIT  ((uint32)0xffU << 8U)
#define FV_SPI_SCK_CHK_UPPER_LIMIT(v) \
  (((uint32)(v) << 8U) & FM_SPI_SCK_CHK_UPPER_LIMIT)
#define GFV_SPI_SCK_CHK_UPPER_LIMIT(v) \
  (((uint32)(v) & FM_SPI_SCK_CHK_UPPER_LIMIT) >> 8U)

#define FM_SPI_SCK_CHK_LOWER_LIMIT  ((uint32)0xffU << 0U)
#define FV_SPI_SCK_CHK_LOWER_LIMIT(v) \
  (((uint32)(v) << 0U) & FM_SPI_SCK_CHK_LOWER_LIMIT)
#define GFV_SPI_SCK_CHK_LOWER_LIMIT(v) \
  (((uint32)(v) & FM_SPI_SCK_CHK_LOWER_LIMIT) >> 0U)

#define SPI_FH_CHK_OFF  0x9cU

#define FM_SPI_FH_CHK_UPPER_LIMIT  ((uint32)0xffffU << 16U)
#define FV_SPI_FH_CHK_UPPER_LIMIT(v) \
  (((uint32)(v) << 16U) & FM_SPI_FH_CHK_UPPER_LIMIT)
#define GFV_SPI_FH_CHK_UPPER_LIMIT(v) \
  (((uint32)(v) & FM_SPI_FH_CHK_UPPER_LIMIT) >> 16U)

#define FM_SPI_FH_CHK_LOWER_LIMIT  ((uint32)0xffffU << 0U)
#define FV_SPI_FH_CHK_LOWER_LIMIT(v) \
  (((uint32)(v) << 0U) & FM_SPI_FH_CHK_LOWER_LIMIT)
#define GFV_SPI_FH_CHK_LOWER_LIMIT(v) \
  (((uint32)(v) & FM_SPI_FH_CHK_LOWER_LIMIT) >> 0U)

#define SPI_TX_FIFO_CMD_OFF  0x1000U

#define SPI_TX_FIFO_DATA_OFF  0x2000U

#define SPI_RX_FIFO_DATA_OFF  0x3000U


#endif  /* SPI_REG_H */
/** End of file */

